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1

Delay sensing for long-term variations and defects monitoring in safety–critical applications

J. C. Vazquez, V. Champac, A. M. Ziesemer, R. Reis, I. C. Teixeira, M. B. Santos, J. P. Teixeira

Journal:

Analog Integrated Circuits and Signal Processing

Year:

2012

Language:

english

File:

PDF, 1.03 MB

english, 2012

2

IDDQ Testing of Opens in CMOS SRAMs

Victor H. Champac, José Castillejos, Joan Figueras

Journal:

Journal of Electronic Testing

Year:

1999

Language:

english

File:

PDF, 79 KB

english, 1999

3

Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals

Champac, V., Avendano, V., Figueras, J.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2010

Language:

english

File:

PDF, 1.13 MB

english, 2010

4

Resistive bridge defect detection enhancement under parameter variations combining Low VDD and body bias in a delay based test

Hector Villacorta, Victor Champac, Sebastià Bota, Jaume Segura

Journal:

Microelectronics Reliability

Year:

2012

Language:

english

File:

PDF, 858 KB

english, 2012

5

[IEEE 1991, International Test Conference - Nashville, TN (Oct. 26-30 1991)] 1991, Proceedings. International Test Conference - CURRENT VS. LOGIC TESTING OF GATE OXIDE SHORT, FLOATING GATE AND BRIDGING FAILURES IN CMOS

Rodriguez-Montanes, R., Segura, J.A., Champac, V.H., Figueras, J., Rubio, J.A.

Year:

1991

Language:

english

File:

PDF, 827 KB

english, 1991

6

Testing of Stuck-Open Faults in Nanometer Technologies

Champac, Victor, Vazquez Hernandez, Julio, Barcelo, Salvador, Gomez, Roberto, Hawkins, Chuck, Segura, Jaume

Journal:

IEEE Design & Test of Computers

Year:

2012

Language:

english

File:

PDF, 1003 KB

english, 2012

7

[IEEE 2008 IEEE International Symposium on Circuits and Systems - ISCAS 2008 - Seattle, WA, USA (2008.05.18-2008.05.21)] 2008 IEEE International Symposium on Circuits and Systems - A design methodology for logic paths tolerant to local intra-die variations

Iparraguirre-Cardenas, Daniel, Garcia-Gervacio, Jose L., Champac, Victor

Year:

2008

Language:

english

File:

PDF, 198 KB

english, 2008

8

Screening small-delay defects using inter-path correlation to reduce reliability risk

García-Gervacio, José L., Nocua, Alejandro, Champac, Victor

Journal:

Microelectronics Reliability

Year:

2015

Language:

english

File:

PDF, 1.51 MB

english, 2015

9

Early Selection of Critical Paths for Reliable NBTI Aging-Delay Monitoring

Gomez, Andres F., Champac, Victor

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2016

Language:

english

File:

PDF, 2.71 MB

english, 2016

10

[IEEE 2002 IEEE International Symposium on Circuits and Systems - Phoenix-Scottsdale, AZ, USA (26-29 May 2002)] 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) - A new technique for noise-tolerant pipelined dynamic digital circuits

Mendoza-Hernandez, F., Linares, M., Champac, V.H., Diaz-Sanchez, A.

Year:

2002

Language:

english

File:

PDF, 293 KB

english, 2002

11

[IEEE 2004 IEEE International Symposium on Circuits and Systems - Vancouver, BC, Canada (23-26 May 2004)] 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) - An improved technique to increase noise-tolerance in dynamic digital circuits

Mendoza-Hernandez, F., Linares, M., Champac, V.H.

Year:

2004

Language:

english

File:

PDF, 294 KB

english, 2004

12

[IEEE 2004 IEEE International Symposium on Circuits and Systems - Vancouver, BC, Canada (23-26 May 2004)] 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) - The noise immunity of dynamic digital circuits with technology scaling

Mendoza-Hernandez, F., Linares, M., Champac, V.H.

Year:

2004

Language:

english

File:

PDF, 288 KB

english, 2004

13

[Frontiers in Electronic Testing] Timing Performance of Nanometer Digital Circuits Under Process Variations Volume 39 || Designing with FinFETs and Process Variation Impact

Champac, Victor, Garcia Gervacio, Jose

Year:

2018

Language:

english

File:

PDF, 1.45 MB

english, 2018

14

An Efficient Metric-Guided Gate Sizing Methodology for Guardband Reduction Under Process Variations and Aging Effects

Gomez, Andres, Champac, Victor

Journal:

Journal of Electronic Testing

Year:

2019

File:

PDF, 1.48 MB

2019

15

[IEEE 2019 IEEE Latin American Test Symposium (LATS) - Santiago, Chile (2019.3.11-2019.3.13)] 2019 IEEE Latin American Test Symposium (LATS) - A Semi-analytical Model for Interconnect Open Defects in FinFET Logic Cells

Forero, Freddy, Galliere, Jean-Marc, Renovell, Michel, Champac, Victor

Year:

2019

Language:

english

File:

PDF, 826 KB

english, 2019

16

[IEEE 2019 IEEE Latin American Test Symposium (LATS) - Santiago, Chile (2019.3.11-2019.3.13)] 2019 IEEE Latin American Test Symposium (LATS) - Identification of Logic Paths Influenced by Severe Coupling Capacitances

Meza-Ibarra, I. D., Champac, V., Gomez-Fuentes, R., Noriega, J. R., Vera-Marquina, A.

Year:

2019

Language:

english

File:

PDF, 112 KB

english, 2019

17

Gate Sizing Methodology with a Novel Accurate Metric to Improve Circuit Timing Performance under Process Variations

Perez-Rivera, Zahira, Tlelo-Cuautle, Esteban, Champac, Victor

Journal:

Year:

2020

File:

PDF, 1.08 MB

2020

18

Exploiting magnetic sensing capabilities of Short Split-Drain MAGFETs

Gerard F. Santillan-Quiñonez, Victor Champac, Roberto S. Murphy

Journal:

Solid-State Electronics

Year:

2010

Language:

english

File:

PDF, 843 KB

english, 2010

19

Quiescent current analysis and experimentation of defective CMOS circuits

J. A. Segura, V. H. Champac, R. Rodríguez-Montañés, J. Figueras, J. A. Rubio

Journal:

Journal of Electronic Testing

Year:

1992

Language:

english

File:

PDF, 1.26 MB

english, 1992

20

A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines

Roberto Gómez, Alejandro Girón, Victor H. Champac

Journal:

Journal of Electronic Testing

Year:

2008

Language:

english

File:

PDF, 315 KB

english, 2008

21

Computing the Detection Probability for Small Delay Defects of Nanometer ICs

José L. García-Gervacio, Victor Champac

Journal:

Journal of Electronic Testing

Year:

2011

Language:

english

File:

PDF, 562 KB

english, 2011

22

Guest Editorial

Marcelo Lubaszewski, Victor Champac

Journal:

Journal of Electronic Testing

Year:

2001

Language:

english

File:

PDF, 27 KB

english, 2001

23

Detectability Conditions of Full Opens in the Interconnections

Antonio Zenteno, Victor H. Champac, Joan Figueras

Journal:

Journal of Electronic Testing

Year:

2001

Language:

english

File:

PDF, 491 KB

english, 2001

24

Guest Editorial

Victor Champac, Ingrid Jansch Porto

Journal:

Journal of Electronic Testing

Year:

2003

Language:

english

File:

PDF, 26 KB

english, 2003

25

Guest Editorial

Fabian Vargas, Victor Champac

Journal:

Journal of Electronic Testing

Year:

2004

Language:

english

File:

PDF, 29 KB

english, 2004

26

Test of data retention faults in CMOS SRAMs using special DFT circuitries

Champac, V.H., Avendano, V.

Journal:

IEE Proceedings - Circuits Devices and Systems

Year:

2004

Language:

english

File:

PDF, 1.39 MB

english, 2004

27

Electrical model of the floating gate defect in CMOS ICs: implications on IDDQ testing

Champac, V.H., Rubio, A., Figueras, J.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

1994

Language:

english

File:

PDF, 1.02 MB

english, 1994

28

Process Variations-Aware Statistical Analysis Framework for Aging Sensors Insertion

Vazquez, J. C., Champac, V., SemiÃ£o, J., Teixeira, I. C., Santos, M. B., Teixeira, J. P.

Journal:

Journal of Electronic Testing

Year:

2013

Language:

english

File:

PDF, 539 KB

english, 2013

29

[IEEE 2011 IEEE VLSI Test Symposium (VTS) - Dana Point, CA, USA (2011.05.1-2011.05.5)] 29th VLSI Test Symposium - A new methodology for realistic open defect detection probability evaluation under process variations

Moreno, Jesus, Champac, Victor, Renovell, Michel

Year:

2011

Language:

english

File:

PDF, 754 KB

english, 2011

30

[IEEE 2012 IEEE 30th VLSI Test Symposium (VTS) - Maui, HI, USA (2012.04.23-2012.04.25)] 2012 IEEE 30th VLSI Test Symposium (VTS) - Small-delay defects detection under process variation using Inter-Path Correlation

Galarza-Medina, Francisco J., Garcia-Gervacio, Jose L., Champac, Victor, Orailoglu, Alex

Year:

2012

Language:

english

File:

PDF, 751 KB

english, 2012

31

[IEEE 2010 15th IEEE European Test Symposium (ETS) - Praha, Czech Republic (2010.05.24-2010.05.28)] 2010 15th IEEE European Test Symposium - Computing the detection of Small Delay Defects caused by resistive opens of nanometer ICs

Garcia-Gervacio, Jose L., Champac, Victor

Year:

2010

Language:

english

File:

PDF, 405 KB

english, 2010

32

[IEEE 2010 IEEE 16th International On-Line Testing Symposium (IOLTS 2010) - Corfu, Greece (2010.07.5-2010.07.7)] 2010 IEEE 16th International On-Line Testing Symposium - Predictive error detection by on-line aging monitoring

Vazquez, J. C., Champac, V., Ziesemer, A. M., Reis, R., Semiao, J., Teixeira, I. C., Santos, M. B., Teixeira, J. P.

Year:

2010

Language:

english

File:

PDF, 944 KB

english, 2010

33

[IEEE 2010 28th VLSI Test Symposium (VTS) - Santa Cruz, CA, USA (2010.04.19-2010.04.22)] 2010 28th VLSI Test Symposium (VTS) - Low-sensitivity to process variations aging sensor for automotive safety-critical applications

Vazquez, J. C., Champac, V., Ziesemer, A. M., Reis, R., Teixeira, I. C., Santos, M. B., Teixeira, J. P.

Year:

2010

Language:

english

File:

PDF, 858 KB

english, 2010

34

[IEEE 2011 IEEE VLSI Test Symposium (VTS) - Dana Point, CA, USA (2011.05.1-2011.05.5)] 29th VLSI Test Symposium - Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensors

Martins, C. V., Semiao, J., Vazquez, J. C., Champac, V., Santos, M., Teixeira, I. C., Teixeira, J. P.

Year:

2011

Language:

english

File:

PDF, 981 KB

english, 2011

35

[IEEE Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004. - Corsica, France (23-26 May 2004)] Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004. - Signal integrity verification using high speed monitors

Avendano, V., Champac, V., Figueras, J.

Year:

2004

Language:

english

File:

PDF, 674 KB

english, 2004

36

[IEEE 2012 13th Latin American Test Workshop - LATW - Quito, Ecuador (2012.04.10-2012.04.13)] 2012 13th Latin American Test Workshop (LATW) - Low voltage testing for interconnect opens under process variations

Moreno, Jesus, Champac, Victor, Renovell, Michel

Year:

2012

Language:

english

File:

PDF, 1.10 MB

english, 2012

37

[IEEE Comput. Soc. Press 13th IEEE VLSI Test Symposium - Princeton, NJ, USA (30 April-3 May 1995)] Proceedings 13th IEEE VLSI Test Symposium - Testability of floating gate defects in sequential circuits

Champac, V.H., Figueras, J.

Year:

1995

Language:

english

File:

PDF, 579 KB

english, 1995

38

[IEEE 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems - Cancun, Mexico (15-17 March 2000)] Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474) - A symbolic circuit analysis-oriented algorithm for finding a common tree of the current and voltage graphs

Sarmiento-Reyes, L.A., Gonzilez-Castolo, L.O., Champac, V.H.

Year:

2000

Language:

english

File:

PDF, 278 KB

english, 2000

39

[IEEE Comput. Soc. Press 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems - Venice, Italy (27-29 Oct. 1993)] Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems - Analysis of the floating gate defect in CMOS

Champac, V.H., Rubio, A., Figueras, J.

Year:

1993

Language:

english

File:

PDF, 408 KB

english, 1993

40

[IEEE 2013 14th Latin American Test Workshop - LATW - Cordoba, Argentina (2013.04.3-2013.04.5)] 2013 14th Latin American Test Workshop - LATW - Bridge defect detection in nanometer CMOS circuits using Low VDD and body bias

Villacorta, Hector, Garcia-Gervacio, Jose, Champac, Victor, Bota, Sebastia, Martinez, Jaime, Segura, Jaume

Year:

2013

Language:

english

File:

PDF, 1.79 MB

english, 2013

41

[IEEE European Test Symposium (ETS'05) - Tallinn, Estonia (22-25 May 2005)] European Test Symposium (ETS'05) - Testing of Resistive Opens in CMOS Latches and Flip-Flops

Champac, V.H., Zenteno, A., Garcia, J.L.

Year:

2005

Language:

english

File:

PDF, 244 KB

english, 2005

42

[IEEE Comput. Soc 18th IEEE VLSI Test Symposium - Montreal, Que., Canada (30 April-4 May 2000)] Proceedings 18th IEEE VLSI Test Symposium - Detectability conditions for interconnection open defects

Champac, V.H., Zenteno, A.

Year:

2000

Language:

english

File:

PDF, 222 KB

english, 2000

43

[IEEE 2009 10th Latin American Test Workshop - Rio de Janeiro, Brazil (2009.03.2-2009.03.5)] 2009 10th Latin American Test Workshop - A modern look at the CMOS stuck-open fault

Gomez, Roberto, Champac, Victor, Hawkins, Chuck, Segura, Jaume

Year:

2009

Language:

english

File:

PDF, 419 KB

english, 2009

44

[IEEE 2009 27th IEEE VLSI Test Symposium (VTS) - Santa Cruz, CA, USA (2009.05.3-2009.05.7)] 2009 27th IEEE VLSI Test Symposium - Stuck-Open Fault Leakage and Testing in Nanometer Technologies

Vazquez, Julio, Champac, Victor, Hawkins, Chuck, Segura, Jaume

Year:

2009

Language:

english

File:

PDF, 1.16 MB

english, 2009

45

[IEEE 2009 15th IEEE International On-Line Testing Symposium (IOLTS 2009) - Sesimbra-Lisbon, Portugal (2009.06.24-2009.06.26)] 2009 15th IEEE International On-Line Testing Symposium - Detectability analysis of small delays due to resistive opens considering process variations

Garcia-Gervacio, Jose L., Champac, Victor

Year:

2009

Language:

english

File:

PDF, 139 KB

english, 2009

46

[IEEE 13th Asian Test Symposium - Kenting, Taiwan (15-17 Nov. 2004)] 13th Asian Test Symposium - Analysis and Attenuation Proposal in Ground Bounce

Zenteno, A., Champac, V.H., Renovell, M., Azais, F.

Year:

2004

Language:

english

File:

PDF, 114 KB

english, 2004

47

[IEEE Comput. Soc Proceedings. XI Brazilian Symposium on Integrated Circuit Design (Cat. No.98EX216) - Rio de Janeiro, Brazil (30 Sept.-3 Oct. 1998)] Proceedings. XI Brazilian Symposium on Integrated Circuit Design (Cat. No.98EX216) - A graph-oriented CAD tool for establishing the topological diagnostic conditions of analogue circuits

Sarmiento-Reyes, A., Gutierrez-de Anda, M.A., Champac, V.H.

Year:

1998

Language:

english

File:

PDF, 62 KB

english, 1998

48

[IEEE 2014 15th Latin American Test Workshop - LATW - Fortaleza, Brazil (2014.3.12-2014.3.15)] 2014 15th Latin American Test Workshop - LATW - Possibilities of defect-size magnification for testing resistive-opens in nanometer technologies

Garcia-Gervacio, Jose L., Martinez-Castillo, Jaime, Champac, Victor

Year:

2014

Language:

english

File:

PDF, 171 KB

english, 2014

49

[IEEE Comput. Soc 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Monterey, CA, USA (3-5 Oct. 2005)] 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) - Test of interconnection opens considering coupling signals

Gomez, R., Giron, A., Champac, V.

Year:

2005

Language:

english

File:

PDF, 291 KB

english, 2005

50

Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops

Zenteno Ramirez, Antonio, Espinosa, Guillermo, Champac, Victor

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2007

Language:

english

File:

PDF, 684 KB

english, 2007